Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!gem.mps.ohio-state.edu!samsung!uunet!philmtl!atha!aunro!myrias!dragos!ruiu
From: ruiu@dragos.uucp (dragos)
Newsgroups: comp.arch
Subject: High speed bus on the new MIPS R6000 box
Keywords: R6000 MIPS bus bandwith
Message-ID: <1989Nov21.032355.5779@dragos.uucp>
Date: 21 Nov 89 03:23:55 GMT
Reply-To: ruiu@dragos.UUCP (dragos)
Organization: Orbital Mind Control Lasers, Inc.
Lines: 29

After listening to an excellent talk by John Mashey at a local user
group meeting, in which he gave some very interesting details of the new
"enterprise" server box based on the ECL R6000, I was left wondering
a few things.

In the box, the chip runs at 67Mhz, and the backplane runs at 270MB/sec.
The bus is 32 bits wide, and 270Mb (255.6 actually) is needed to supply
one piece of data on every clock cycle. The question that comes to mind
immediately: How many hoops did the designers have to jump through to
achieve this ? Does anyone have any information on just how difficult
it is to do a design at this speed ? (I'm told by those who have done it
that even working at 40MHz is a pain because of capacitance problems.)
Are bus connectors a problem at high speeds ? 

This 270MB/sec. figure was surprising to me - previous high speed busses I
had seen were in the range of 80-128 MB/sec. Am I just behind the times ?

As well, what kind of memory designs can steadily deliver hundreds of MB/sec. ?
We were told that the MIPS box has 594K of cache (67Mhz, hmmm... 20ns I assume)
so maybe all reads and writes are page mode and each memory board has
a cache too ?

I wonder how much cache misses cost at 67MHz. I wonder how often they happen
in the MIPS design.

-- 
Dragos Ruiu (ruiu@dragos.uucp)     All system administrators should hand out   
alberta!dragos!ruiu                a bottle of valium with every news-reader
uunet!myrias!dr                    man page.