Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!purdue!decwrl!henry.jpl.nasa.gov!elroy.jpl.nasa.gov!gryphon!vector!attctc!linimon
From: linimon@attctc.Dallas.TX.US (Mark Linimon)
Newsgroups: comp.arch
Subject: Re: I/O processors
Summary: quibble
Message-ID: <10347@attctc.Dallas.TX.US>
Date: 26 Nov 89 16:31:08 GMT
References: <1128@m3.mfci.UUCP> <1989Nov22.175128.24910@ico.isc.com> <3893@scolex.sco.COM> <39361@lll-winken.LLNL.GOV> <3898@scolex.sco.COM> <32146@winchester.mips.COM>
Reply-To: linimon@attctc.Dallas.TX.US (Mark Linimon)
Followup-To: comp.arch
Distribution: usa
Organization: The Unix(R) Connection BBS, Dallas, Tx
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In article <32146@winchester.mips.COM> mash@mips.COM writes:
>d) Many of the current high-performance I/O boards have 68020s, already,
>as in some of Interphase's products.

Change this to "almost all of" and I'll go along with it.  The only
non-MPU-based VMEbus I/O boards that I can think of, offhand, are
not in the "high-performance" category.  (I am sure a few non-MPU
or bit-slice designs exist; I'm claiming that they are now the exception,
not the rule).

Mark Linimon
Software Engineering
Mizar, Inc.
linimon@mizarvme

disclaimer: I disclaim that I even said this.