Path: utzoo!utgpu!watmath!att!rutgers!ucsd!usc!samsung!uunet!tank!eecae!netnews.upenn.edu!eniac.seas.upenn.edu!silver
From: silver@eniac.seas.upenn.edu (Andy Silverman)
Newsgroups: comp.binaries.ibm.pc.d
Subject: Re: RISC vs CISC
Message-ID: <17075@netnews.upenn.edu>
Date: 17 Nov 89 04:31:56 GMT
References: <29806@iuvax.cs.indiana.edu>
Sender: news@netnews.upenn.edu
Reply-To: silver@eniac.seas.upenn.edu.UUCP (Andy Silverman)
Distribution: comp.binaries.ibm.pc.d
Organization: University of Pennsylvania
Lines: 11

I may be mistaken, but I thought the whole idea behind RISC was to make
the chips simple so that they COULD be run at blinding speeds.  Since RISC
instructions don't do very much, they'd have to be run extremely fast to
be useful.  Isn't it easier to make a simple chip run really fast than a
very complex one?

+-----------------------+-----------------------------------------+
| Andy Silverman        | Internet:   silver@eniac.seas.upenn.edu |
| "All stressed out and | Compu$erve: 72261,531                   |
|  nobody to choke."    |                                         |         
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