Path: utzoo!mnetor!tmsoft!torsqnt!jarvis.csri.toronto.edu!rutgers!ucsd!usc!samsung!uunet!kddlab!titcca!ccut!s.u-tokyo!hideki
From: hideki@is.s.u-tokyo.ac.jp (YOSHIDA Hideki)
Newsgroups: comp.binaries.ibm.pc.d
Subject: Re: RISC vs CISC
Message-ID: <264@utsun.s.u-tokyo.ac.jp>
Date: 18 Nov 89 02:53:03 GMT
References: <29806@iuvax.cs.indiana.edu>
Sender: news@s.u-tokyo.ac.jp
Reply-To: hideki@is.s.u-tokyo.ac.jp
Distribution: comp.binaries.ibm.pc.d
Organization: Dept. of Information Science, the Univ. of Tokyo, Japan.
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In-reply-to: sl179060@silver.bacs.indiana.edu's message of 16 Nov 89 18:02:18 GMT

>when I ran the MIPS (Chips & Tech) benchmark, I got a disappointing 2.5 - 3.00
>MIPS. Does that mean that the 'average' 286 instruction takes 8 cycles?

  No.  $ MIPS = 1 / average execution time of a instruction $ is an
old-fashioned definition.  In most cases, MIPS value is obtained by
comparing the result of a benchmark with that of VAX-11/780, so that
RISC chips will be evaluated more correctly.
--
					Hideki Yoshida

					Department of Information Science
					Faculty of Science
					The University of Tokyo

					hideki@is.s.u-tokyo.ac.jp