Path: utzoo!attcan!uunet!samsung!usc!apple!bridge2!mbt
From: mbt@bridge2.ESD.3Com.COM (Brad Turner)
Newsgroups: comp.binaries.ibm.pc.d
Subject: Re: RISC vs CISC
Message-ID: <1104@bridge2.ESD.3Com.COM>
Date: 17 Nov 89 17:02:55 GMT
References: <29806@iuvax.cs.indiana.edu> <17075@netnews.upenn.edu>
Distribution: comp.binaries.ibm.pc.d
Organization: 3Com Corp., Mt. View, CA
Lines: 16

Based on my limited knowledge in the subject area I thought that the
distinguishing characteristics of a RISC chip were the following:
    o  Hardcoded logic.
    o  All instruction execute in 1 clock cycle
It is the combination of the two above items that generally require
the instruction set to be small. I suppose in theory you could have
a large number of instructions and as long as all the instructions
adhered to the above constraints the chip could be considered RISC.


-brad-

-- 
v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v^v
Brad Turner |2081 Shoreline Blvd.|(415) 969-2099 ext 217  | I speak for myself
3Com Corp.  |Mtn. View, CA 94043 |mbt@bridge2.ESD.3Com.Com| NOT for my employer