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From: cs9a-ax@dorothy.Berkeley.EDU (Mike Morrison)
Newsgroups: comp.binaries.ibm.pc.d
Subject: Re: RISC vs CISC
Message-ID: <19693@pasteur.Berkeley.EDU>
Date: 17 Nov 89 22:01:35 GMT
References: <29806@iuvax.cs.indiana.edu> <17075@netnews.upenn.edu> <1104@bridge2.ESD.3Com.COM>
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Reply-To: cs9a-ax@dorothy.Berkeley.EDU.UUCP (Mike Morrison)
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In article <1104@bridge2.ESD.3Com.COM> mbt@bridge2.ESD.3Com.COM (Brad Turner) writes:
>Based on my limited knowledge in the subject area I thought that the
>distinguishing characteristics of a RISC chip were the following:
>    o  Hardcoded logic.

>    o  All instruction execute in 1 clock cycle

I don't think so -- any instruction that loads something from memory still
requires more than one clock -- one to put the address on the bus and one
to receive the data, plus any other overhead.

Mike Morrison
cs9a-ax@dorothy.berkeley.edu