Xref: utzoo comp.lsi:887 comp.lsi.cad:325
Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!cs.utexas.edu!oakhill!dover!darla!waters
From: waters@darla.sps.mot.com (Strawberry Jammer)
Newsgroups: comp.lsi,comp.lsi.cad
Subject: Re: Circuit Simulator Benchmarks
Summary: netlist standard
Keywords: benchmarks, public, circuits, spice
Message-ID: <1955@dover.sps.mot.com>
Date: 22 Nov 89 15:49:24 GMT
References: <5780@alvin.mcnc.org>
Sender: news@dover.sps.mot.com
Reply-To: waters@darla.sps.mot.com (Strawberry Jammer)
Organization: Hacker's haven
Lines: 55

In article <5780@alvin.mcnc.org> kenkel@mcnc.org (Stephen Kenkel) writes:
}I would like to propose that a publicly available collection be 
}established of circuits.  The circuits would be selected to
}include tough circuits for traditional simulators (bipolar, 
}opamps, feedback, bi-stable, etc), very large circuits, circuits
}which are suitable for waveform relaxation, circuits which
}give rise to unknown states with timing simulators, etc.

An excellent idea! With the usual caveats as to generality and applicability
of the test cases. As an industrial CAD type I would also urge the inclusion
of some realisticly sized models. For example a portion of a microprocessor
with analog I/O - maybe 1000+ (10K+ ?) devices.

Far too often I see papers talking about "large" behavioral simulators or
routers which have been tested on 100 or 200 gates and are totally useless
with 500K+ which is where such things are useful today.

}1.   Freely distributable.  This should not be too much of a problem,
}since it is difficult to reverse engineer a circuit from the flattened
}netlist.

I think this implies some "diddling" of models and process parameters. I know
we (Motorola) would not give out any accurate process models and I'm sure the
other manufacturers feel the same way.

}2.  In SPICE compatabile netlist form.  (For lack of a more universal
}standard)

I would suggest EDIF V 2 0 0 which is used for netlists throughout the ASIC
industry. There are even examples in some of the older documentation about
translating SPICE netists to/from EDIF, it is a very straightforward mapping.

}3.  Use a standard device model:  SPICE Level I, II, III, IV or BJT.
}Many industrial circuits use custom device  models, which again
}confuses comparisons.

Yes (see 1 above). It would however have to be of "equivalent" complexity to
models in actual use. The best way of achieving this might be by having a
number of device engineers at IC companies comment on and validate the model
being used.

}4.  MOST important:  include an output file containing what is 
}believed to be a correct simulation at the circuit level, for
}comparison purposes.  If possible, enought information should be
}given so that SPICE, HSPICE, PSPICE, or whatever can be re-run to
}verify the correctness of the output.

Again I think EDIF V 2 0 0 might be useful here, possibly one of the EDIF
Test proposals for handling test vectors might be worth testing too. It
is definitly worth some trouble to use a common standard for both stimuli and
output analysis.

           *Mike Waters    AA4MW/7  waters@dover.sps.mot.com *
Justice is incidental to law and order.
		-- J. Edgar Hoover