Xref: utzoo comp.lsi:890 comp.lsi.cad:330 Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uunet!mcsun!ukc!mucs!manse.cad.cs.man.ac.uk!whitaker From: whitaker@manse.cad.cs.man.ac.uk (Nigel Whitaker) Newsgroups: comp.lsi,comp.lsi.cad Subject: Re: Circuit Simulator Benchmarks (also >= gate level) Summary: Gate level and above benchmarks - including poll on languages Keywords: simulation benchmarks EDIF ELLA VHDL Message-ID: <61.256c4a76@manse.cad.cs.man.ac.uk> Date: 23 Nov 89 19:52:22 GMT References: <5780@alvin.mcnc.org> Reply-To: whitaker@cs.man.ac.uk Organization: Department of Computer Science, University of Manchester Lines: 94 Hello folks, I saw Stephens request for circuit simulation benchmarks, and thought I would add my 1/2 pence (:-) worth, in my hunt for gate level (and above) simulation benchmarks. In article <5780@alvin.mcnc.org>, kenkel@mcnc.org (Stephen Kenkel) writes: > It has struck me recently that there does not seem to > exist a good, standard, publicly available collection of > benchmark circuits for circuit and timing level simulators. The same situation is also true for simulators at the gate level and above. Indeed I, others (I have seen requests from "Jack V. Briner" and gld@cunixd.cc.columbia.edu) have made requests for benchmarks to the net. I assume others working on simulation algorithms, or parallel simulation algorithms, would also benefit from a set of standard benchmarks. The only `standard' simulation benchmarks have been those from ISCAS 85 & 89. These were not intended as simulation benchmarks and to my mind are very poor examples for anything but very simplistic gate level simulations. > I would like to propose that a publicly available collection be > established of circuits. The circuits would be selected to > include tough circuits for traditional simulators (bipolar, > opamps, feedback, bi-stable, etc), very large circuits, circuits > which are suitable for waveform relaxation, circuits which > give rise to unknown states with timing simulators, etc. My wish list would include: gate, functional, behavioural descriptions of large and small, ASICs, PCB designs and possibly microprocessors, or even complete systems?.... > 2. In SPICE compatabile netlist form. (For lack of a more universal > standard) > > 3. Use a standard device model: SPICE Level I, II, III, IV or BJT. > Many industrial circuits use custom device models, which again > confuses comparisons. There seems to be an overlap of standards at the gate level and above. The `standards' in effect in this country include: VHDL, ELLA and EDIF (logicmodel and netlist are probably applicable here) Any others????? I would like to conduct an informal email survey to determine which of these languages are in use, and which could provide the greatest number of benchmark circuits. This would help me, and hopefully others, when trying to find/use benchmarks. Do you use one, or more, of these languages? Do you intend to switch to using one of these? Do you have any opinions as to which language a set of simulation benchmarks should use? Do you have anything at all to contribute on the subject? Please email responses to: whitaker@cs.man.ac.uk, I will summarise any responses back to the net (please state if you require any information supplied to be treated in confidence). > 4. MOST important: include an output file containing what is > believed to be a correct simulation at the circuit level, for > comparison purposes. If possible, enought information should be > given so that SPICE, HSPICE, PSPICE, or whatever can be re-run to > verify the correctness of the output. I agree with this part, there needs to be a set of input waveforms, and output ones, in order to test the correctness of the simulation. What standards could be used in this area? > DISCLAIMER: > MCNC distributes a circuit level simulator (CAzM), and > has a vested interest in the benchmarking of such programs. The same applies here, I am working on workload distribution algorithms for parallel simulation (*currently* using both ELLA and EDIF for various forms of input), and would dearly like some large benchmark circuits. Anything I receive in the way of benchmarks, with the suppliers permission, I would be quite happy to make available to anyone on the net. Thnaks for your time, Nigel -- -------------------------------------------------------------------------------- Nigel Whitaker, Room IT202, Department of Computer Science, University of Manchester, Oxford Road, Manchester, M13 9PL, U.K. Tel: (061) 275 6163 Fax: (061) 275 6280 EMAIL: whitaker@cs.man.ac.uk or ...!uunet!mcsun!ukc!mucs!nigelw