Path: utzoo!attcan!uunet!ncrlnk!ncrcae!hubcap!brooks
From: brooks@maddog.llnl.gov (Eugene Brooks)
Newsgroups: comp.parallel
Subject: Re: IPSC Communications
Keywords: IPCS Parallel
Message-ID: <7130@hubcap.clemson.edu>
Date: 20 Nov 89 14:22:51 GMT
Sender: fpst@hubcap.clemson.edu
Lines: 24
Approved: parallel@hubcap.clemson.edu

In article <7110@hubcap.clemson.edu> coop@cerc.wvu.wvnet.edu writes:
>A little while ago I saw a video lecture by a designer from Intel that
>predicted that the next generation of their hypercube IPSC systems is going
>to use a two-dimensional grid communications scheme with a more sophisticated
>router instead of their currently n-cube communication scheme. Wouldn't this
>make the architecture less flexible and expandable, besides making it necessary
>to restructure the instruction set ? Does anyone have any details on this ?
A 2-D grid is more expandable than a hypercube, in that the node only
requires 4 ports independent of machine size.  Bandwidth across a bisection
of the machine is less, but this does not in any way change the
instruction set.  If the network wormhole routes you just send a message
to the destination processor and thats it.  There are just a lot more ways
for the message to run into a conflict on the 2-D grid, but it will eventually
get to its destination.  It is interesting to note that the orginal message
passing machine at Caltech was proposed as a grid, not a hypercube.  The
Computer scientists there thought that hypercubes were prettier at the time
and forced the physicists to learn Grey codes to get their physics problem
mappings done.

With regards to the possible use of i860,  I am sure that Intel would only
use their best in a machine for serious supercomputing.

          No one will survive the attack of the Killer Micros
brooks@maddog.llnl.gov, brooks@maddog.uucp