Path: utzoo!attcan!uunet!ncrlnk!ncrcae!hubcap!pase
From: pase@orville.nas.nasa.gov (Douglas M. Pase)
Newsgroups: comp.parallel
Subject: Re: IPSC Communications
Keywords: iPSC Parallel
Message-ID: <7142@hubcap.clemson.edu>
Date: 20 Nov 89 21:53:46 GMT
Sender: fpst@hubcap.clemson.edu
Lines: 27
Approved: parallel@hubcap.clemson.edu

In article <7110@hubcap.clemson.edu> coop@cerc.wvu.wvnet.edu writes:
>Wouldn't [Intel's two-dimensional grid communications scheme] make the
>architecture less flexible and expandable [than the older n-cube topology],
>besides making it necessary to restructure the instruction set?

A lot of Intel's ideas are based (at least initially) on William Dally's PhD.
thesis.  Grossly simplified, the idea is that one can trade the wire layout
complexity of an n-cube arrangement for higher bandwidth connections (more +
shorter wires) in a grid/torus.  Most important, he shows that such trades
favor the 2d arrangements.  With a simple argument it is easily shown that
a grid/torus constructed in that way has lower latency and contention than
an n-cube, *even for problems which prefer an n-cube*.  The question I still
have is whether Intel is allocating the wire space as Dally recommends, or if
they're using low wire-count connections to connect the grid PEs as they do
for the current n-cube machines.  The performance improvements DEPEND on the
higher wire-count connections.

No programming changes are necessary.  Routing has always been handled by the
system.

>P.S. is an i860-based iPSC in the future?
Well, not so much the future as the present...
Dr. Douglas M. Pase				Computer Sciences Corporation
95 Sierra Vista Ave				NAS MS 258-6
Mountain View, CA  94043			NASA Ames Research Center
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pase@orville.nas.nasa.gov			(415) 694-6394