Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!shadooby!samsung!brutus.cs.uiuc.edu!usc!rutgers!cbmvax!daveh
From: daveh@cbmvax.UUCP (Dave Haynie)
Newsgroups: comp.sys.amiga.tech
Subject: Re: Bus Latency
Message-ID: <8651@cbmvax.UUCP>
Date: 20 Nov 89 18:33:28 GMT
References: <322@blenheim.nsc.com>
Organization: Commodore Technology, West Chester, PA
Lines: 27

in article <322@blenheim.nsc.com>, waggoner@dtg.nsc.com (Mark Waggoner) says:
> Keywords: bus dma latency

> Does anyone know what the maximum expected latency for a dma
> peripheral on the Amiga bus is?  The recent postings about dma vs.
> non-dma disk controllers mention that dma can be locked out for a long
> time when an overscan screen is being displayed, but how long is "a
> long time?"

Same length of time that the CPU can be locked out -- the length of continuous
custom chip access to the chip bus (eg, the chips always get the chip bus when 
they want it).  In most situations, the maximum continuous chip bus access is
for display fetches for a 640xNx4 screen, and is the length of a horizontal 
scan line.  With heavy blitter and copper activity it's theoretically possible
to eat up the otherwise free time during horizontal blanking, but it's
usually not done.  Now, if you're DMA is directed toward chip memory, getting
the bus will only be the start of your problems, since you'll only have
access during blanking time.  If the DMA activity is to fast memory somewhere,
the DMA latency could very well account for the bulk of the time you spend.

> |  Mark Waggoner   (408) 721-6306           waggoner@dtg.nsc.com     |


-- 
Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests"
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                    Too much of everything is just enough