Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!brutus.cs.uiuc.edu!usc!rutgers!cbmvax!daveh
From: daveh@cbmvax.UUCP (Dave Haynie)
Newsgroups: comp.sys.amiga.tech
Subject: Re: Bus Latency
Message-ID: <8653@cbmvax.UUCP>
Date: 20 Nov 89 19:03:21 GMT
References: <3058@hub.UUCP>
Organization: Commodore Technology, West Chester, PA
Lines: 26

in article <3058@hub.UUCP>, dougp@voodoo.ucsb.edu says:

> Given the  704x440 screen and the other conditions, how does the buss
> arbitraion handle the condition of the 68000 wanting access to chip
> ram, and the DMA wanting access to fast ram? does the bus lock up
> until the chip ram is free preventing the DMA from accessing fast
> ram or is there some more intelegent arbitration going on?

Unfortunately, there's nothing sophisticated done here.  To prevent any
unsightly arbitration delays, the 68000's access to the chip bus is
arbitrated simply by wait stating the 68000.  This is normally a very
good thing, since there's never any arbitration delay when the 68000
wants chip memory and it's OK to get it.  However, when an expansion
device requests the bus, the bus arbiter will give it a grant pretty
quickly, but it must wait until the current cycle is finished before
acknowledging that grant and taking the bus.  Since the 68000 is wait
stated, the cycle doesn't end until the 68000 gets the chip bus. 
Thus the potential for lag, even for DMA devices that aren't interested 
in chip memory.

> Douglas Peale

-- 
Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests"
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                    Too much of everything is just enough