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From: derek@cs.qmc.ac.uk (Derek Coppen)
Newsgroups: comp.sys.transputer
Subject: transputer link hardware
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Date: 24 Nov 89 10:45:04 GMT
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Transputers use a PLL to generate a high frequency clock
(100MHz I believe) to time in the serial data just the same as
a conventional UART.

In my application I wanted to connect a link adaptor to an
Ethernet controller. The INMOS link adaptors at 20Mbaud
don't go fast enough to support a 10Mbaud ethernet link partly
because of the frame overhead and servicing latency, but mainly
because the adaptors don't support the overlapped acknowledge
protocol. My solution was to implement a double buffered
overlapped ack link adaptor on a Xilinx LCA chip using both edges
of a 40MHZ crystal clock instead of the 100MHz PLL source.
There was enough room left on the chip (the smallest in the
range) to implement a finite state machine to control a 9 bit
bidirectional data bus with read and write strobes to the Seeq8003
ether controller. As a bonus a 20MHz output feeds the manchester
encoder saving an extra crystal.