Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uunet!convex!convexc!patrick
From: patrick@convexc.uucp (Patrick F. McGehearty)
Newsgroups: comp.arch
Subject: Re: High speed bus on the new MIPS R6000 box
Keywords: R6000 MIPS bus bandwith
Message-ID: <3431@convex.UUCP>
Date: 27 Nov 89 04:31:16 GMT
References: <1989Nov21.032355.5779@dragos.uucp>
Sender: news@convex.UUCP
Reply-To: patrick@convex.COM (Patrick F. McGehearty)
Organization: Convex Computer Corporation, Richardson, Tx.
Lines: 15

In article <1989Nov21.032355.5779@dragos.uucp> ruiu@dragos.UUCP (dragos) writes:
>In the box, the chip runs at 67Mhz, and the backplane runs at 270MB/sec.
>The bus is 32 bits wide, and 270Mb (255.6 actually) is needed to supply
>one piece of data on every clock cycle.
>This 270MB/sec. figure was surprising to me - previous high speed busses I
>had seen were in the range of 80-128 MB/sec. Am I just behind the times ?
>
High speed is a relative term (maybe a marketing word :-)
The Convex C2 series supports simultaneous transfers between 4 processors
and memory at 800 Mbytes per second, nominal.  That works out to 200
Mbytes/second per processor.  And that is a 2 year old product.
I am sure that Cray processors have even higher speed buses.

All of which is not to minimize accomplishment of the MIPS R6000 design team.
Buses > 40 MHz are still pretty rare, so involve unusual design problems.


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