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From: mcg@ishark.Berkeley.EDU (Steven McGeady)
Newsgroups: comp.arch
Subject: Re: 55 MIPS & 66 MIPS
Message-ID: <5275@omepd.UUCP>
Date: 28 Nov 89 02:20:22 GMT
References: <31329@winchester.mips.COM> <1358@bnr-rsc.UUCP>
Sender: news@omepd.UUCP
Reply-To: mcg@ishark.Berkeley.EDU (Steven McGeady)
Lines: 29


In article <31329@winchester.mips.COM>, hawkes@mips.COM (John Hawkes) writes:

> The Atlantic Research Corporation, an independent group, has done some
> comparisons between the MIPS R3000 (25-MHz) and a 20-MHz 80960 executing >Ada
> programs (the "Common Avionics Processor Ada Benchmark Suite"), and they
> discovered that the R3000 was usually more than twice as fast on hand-
> coded programs, and overall was more than five times faster on
compiled > > programs.

The 20MHz 960 referred to here is the Military 80960MC part, *not* the
960CA. The 960MC hit silicon in 1985 and has not been upgraded since
then. ARC did not measure the 960CA, even though that would have been
a more representative measurement.  The part measured was running in a
PC/AT plug-in board.  The MIPS system it is being compared to is a full
system with a significantly-sized off-chip cache.

The 960CA would perform approximately 2x *faster* than the MIPS R3000
on the handcoded versions of the benchmarks.  For compiled code, if
the code were written in C, we would also perform approximately 2x
faster.  The code in question was compiled with a beta-release Ada
compiler available last spring.  Mr. Hawkes is doing the expected
in attempting to show MIPS' processor in the best light, but not in
Mr. Mashey's spirit of "full disclosure".  If people are more
interested in these tests, I will see how much information JIAWG will
allow to be released, and release it here.
 
S. McGeady
Intel Corp.


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