Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!tut.cis.ohio-state.edu!ucbvax!ucsd!nosc!marlin!aburto From: aburto@marlin.NOSC.MIL (Alfred A. Aburto) Newsgroups: comp.arch Subject: Re: 55 MIPS & 66 MIPS Message-ID: <1256@marlin.NOSC.MIL> Date: 28 Nov 89 18:21:21 GMT References: <1358@bnr-rsc.UUCP> <31329@winchester.mips.COM> <22303@gryphon.COM> <28107@amdcad.AMD.COM> Reply-To: aburto@marlin.nosc.mil.UUCP (Alfred A. Aburto) Organization: Naval Ocean Systems Center, San Diego Lines: 23 Distribution:comp.arch In article <28107@amdcad.AMD.COM> tim@amd.com (Tim Olson) writes: > >To provide a more fair comparison, I requested the benchmark sources >from Intel, to run on a 30MHz Am29000 board (manufactured by YARC >Systems). This board uses 2-way interleaved, 100ns DRAM memory for >instructions and 35ns SRAM for data. > > -- Tim Olson > Advanced Micro Devices > (tim@amd.com) While your comparative results are very interesting, and useful as a point of reference, I must throw in some words of caution. That is, the individual results are highly dependent upon the machine code generating efficiency of the various compilers used. In order to achieve real useful relative comparisons of performance we must somehow demonstrate that the compilers generate reasonably optimal (or 'typical', or equally degraded :-)) machine code for each benchmark. I know for example the 68030 @ 25 MHz coupled with 'the right stuff' (hardware and compiler) can achieve roughly 10K (V1.1) Dhrystones/sec (as compared to the 5.5K result posted). Al Aburto aburto@marlin.nosc.mil Brought to you by Super Global Mega Corp .com