Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!usc!henry.jpl.nasa.gov!elroy.jpl.nasa.gov!gryphon!scarter
From: scarter@gryphon.COM (Scott Carter)
Newsgroups: comp.arch
Subject: JIAWG benchmarks, R3000, i960CA (was Re: 55 MIPS & 66 MIPS)
Message-ID: <22882@gryphon.COM>
Date: 29 Nov 89 23:25:04 GMT
References: <31329@winchester.mips.COM> <1358@bnr-rsc.UUCP> <5275@omepd.UUCP>
Reply-To: scarter@gryphon.COM (Scott Carter)
Organization: Trailing Edge Technology, Redondo Beach, CA
Lines: 56

In article <5275@omepd.UUCP> mcg@ishark.Berkeley.EDU (Steven McGeady) writes:
>In article <31329@winchester.mips.COM>, hawkes@mips.COM (John Hawkes) writes:
>
>> The Atlantic Research Corporation, an independent group, has done some
>> comparisons between the MIPS R3000 (25-MHz) and a 20-MHz 80960 executing Ada
>> programs (the "Common Avionics Processor Ada Benchmark Suite"), and they
>> discovered that the R3000 was usually more than twice as fast on hand-
>> coded programs, and overall was more than five times faster on
>compiled > > programs.
>
>The 20MHz 960 referred to here is the Military 80960MC part, *not* the
>960CA. The 960MC hit silicon in 1985 and has not been upgraded since
>then. ARC did not measure the 960CA, even though that would have been
>a more representative measurement.

More representative of what?  I agree, I'd love see the 960CA numbers on the
integer JIAWG benchmarks - not to mention a few of our own - but the about
half the benchmark suite is floating point.

Also, contrary to the"typical" embedded system, the JIAWG avionics systems
_do_ need MMUs to implement the multilevel (B3/A1 - ouch!) secure OS
requirements.  The capability addressing of the 960XA was one of it's big 
selling points.

>The part measured was running in a
>PC/AT plug-in board.  The MIPS system it is being compared to is a full
>system with a significantly-sized off-chip cache.

We got numbers of a BiiN 6220, which is [was] a full-sized system.  If
the caches on that system were smaller than on an M/2000 - and they were -
why?  Certainly not to make a cheap system.

>The 960CA would perform approximately 2x *faster* than the MIPS R3000
>on the handcoded versions of the benchmarks.  For compiled code, if
>the code were written in C, we would also perform approximately 2x
	       ^^^^^^^^^^^^
>faster.

Why this caveat, i.e. why not Ada?  Or is it just the lack of a suitable
Ada for the 960CA?

Using a set of Pascal versions of some of the JIAWG benchmarks [developed
by an independent contractor for another program], we got much better
performance out of the Mips than in the Ada version.

>The code in question was compiled with a beta-release Ada
>compiler available last spring.
<...>
>If people are more
>interested in these tests, I will see how much information JIAWG will
>allow to be released, and release it here.
> 
>S. McGeady
>Intel Corp.

Scott Carter


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