Xref: utzoo comp.sys.nsc.32k:744 comp.arch:12659 sci.electronics:8841 Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!usc!apple!vsi1!daver!dlr From: dlr@daver.UU.NET (Dave Rand) Newsgroups: comp.sys.nsc.32k,comp.arch,sci.electronics Subject: Low cost NS32532 system Message-ID: <1989Nov30.225050.2124@daver.UU.NET> Date: 30 Nov 89 22:50:50 GMT Organization: Association for the Prevention of Polar Bears and Kangaroos Lines: 69 Last year, there was great talk about doing a 32532-based system, with all kinds of wizzy features. Most people took note of the suggestions, and some even went so far as to suggest some of their own ideas :-) We, george@wombat.UUCP (George Scolaro) and dlr@daver.UU.NET (Dave Rand) went ahead and did a design. George did the hardware, and I did (am doing :-) the software. The design goal for this board was to produce a home brew design that was as cheap as possible, with the best performance. It does not have external cache, nor does it have parity, nor does it have a wizzy we-do-it-all-for-you bus. It does have all the necessary goods to deliver a good performance, lots of software hacking (and hardware via the SCSI *cheap* expansion) system that will keep you busy during the rainy days... In keeping with the design goal, the schematics, and pal equations and gerber files (if required) are available for the asking. This design is totally free and is there for people that want to hack (in the old style). There is a mailing list for those of you that are interested. Send your requests to: . The PC532 board has the following features: 1 x NS32532 25 Mhz CPU 1 x NS32381 25 Mhz FPU 1 x NS32202 10 Mhz ICU 1 x DP8490 SCSI device that manages a 62 pin XT mechanically compatible 4 slot multimaster bus. This bus can run at up to 3.8 megabytes per second. Multimaster is supported by the DP8490 SCSI device. 1 x AIC6250 SCSI device that connects to a 50 pin SCSI header. This device is intended to connect to hard disk and mag tape media. The AIC6250 supports async and sync SCSI. The interface supports data transfers nables over 4 megabytes per second. 4 x SCN2681 DUARTs. This gives the PC532 8 serial channels, which are all individually connected to interrupt inputs on the ICU. Each DUART generates an INT and in addition a wire or-ed RX ready channel A/ channel B. 1 x 27256 EPROM (200 ns). This EPROM contains any necessary boot firmware. It is intended that a Dallas Semiconductor (or compatible) clock chip/socket be used under the EPROM to give the PC532 a battery backed real time clock. 4/8 megabytes (1 megabit x 8 80ns SIMMs) or 16/32 megabytes (4 megabit x 8 80 ns SIMMs). Page mode dram devices must be used and the design utilizes the page mode access to achieve 0 wait state read (1st access), 0 wait state write, 1 wait state for the rest of a read burst if in page. If not in page a 4 wait state penalty occurs. Two refresh cycles are performed every 30us (to reduce the page break rate). This gives a 50 megabyte/second memory interface (while bursting in page). The board currently runs a modified version of MON16 which enables a 32000 host system to download code, set break points, source level debug etc. Compute performance is roughly 10 X a 32016 based system (ICM3216). I/O performance should be considerably faster. Total of 45 devices, including CPU etc, but excluding the DRAM SIMMs. There are 2 D-speed PAL devices and 3 B-speed PAL devices on the board. All glue logic, buffers and latches are either 74AS or 74ALS technology. The PCB is 6 layers, 13 in x 8 in baby AT form factor. It connects to a standard AT power supply (draws 2.6 Amps typical), has holes to mount in an AT chassis, have 4 XT (mechanical only) slots that will accept XT or AT wirewrap prototype cards (power pins are XT compatible). -- Dave Rand {pyramid|hoptoad|sun|vsi1}!daver!dlr Internet: dlr@daver.uu.net Brought to you by Super Global Mega Corp .com