Path: utzoo!attcan!uunet!tut.cis.ohio-state.edu!rutgers!cbmvax!jesup
From: jesup@cbmvax.UUCP (Randell Jesup)
Newsgroups: comp.arch
Subject: Re: On chip caches (was RISC vs. CISC)
Message-ID: <8801@cbmvax.UUCP>
Date: 3 Dec 89 13:54:03 GMT
References: <8911100815.AA00800@decwrl.dec.com>
Reply-To: jesup@cbmvax.UUCP (Randell Jesup)
Organization: Commodore Technology, West Chester, PA
Lines: 24

In article <8911100815.AA00800@decwrl.dec.com> neideck@kaputt.dec.com (Burkhard Neidecker-Lutz) writes:
>He doesn't count gate delays (go ahead, choose a 0ns technology) but only
>counts the times it takes to get off-chip, off-board, etc.
...
>Makes for little guessing and relatively accurate numbers. It turns out that
>there is a gap of a factor of about 10 to 20 between machines that have
>to go for an external cache each cycle and those that do not have to. The
>limiting factor is the interconnect delay and that cannot be arbitrarily 
>lowered. The whole data is impossible to reproduce here, read the paper.

	As I (and others here on comp.arch) have been saying: interconnect
speed is rapidly becoming a limiting factor for microprocessors (as it
already is for mainframes/supers).  However, the statement that interconnect
delay cannot be arbitrarily lowered is misleading at best.  It can be lowered
in a number of ways (some of which require major changes in packaging/fab and
related changes in chip design - not just a drop-in).  Interconnect delay
cannot be lowered to 0, but then again neither can gate delays.

	Sounds like an interesting paper.

-- 
Randell Jesup, Keeper of AmigaDos, Commodore Engineering.
{uunet|rutgers}!cbmvax!jesup, jesup@cbmvax.cbm.commodore.com  BIX: rjesup  
Common phrase heard at Amiga Devcon '89: "It's in there!"


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