Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!shadooby!samsung!uunet!lotus!esegue!compilers-sender From: larus@primost.wisc.EDU (James Larus) Newsgroups: comp.compilers Subject: Re: register allocation Keywords: chow, chaitin Message-ID: <1989Nov28.031713.13412@esegue.segue.boston.ma.us> Date: 28 Nov 89 03:17:13 GMT References: <1989Nov22.183501.6735@esegue.segue.boston.ma.us> Sender: compilers-sender@esegue.segue.boston.ma.us Reply-To: larus@primost.wisc.EDU (James Larus) Organization: University of Wisconsin--Madison Lines: 10 Approved: compilers@esegue.segue.boston.ma.us Just a note on Bob Scheulen's (microsoft!bobs@beaver) article. There's no reason why Chow's algorithm can't be post-generation (i.e., allocate register for the actual instruction set). I used it that way in the SPUR Lisp compiler. Of course, assembly code for RISC machines looks a lot like intermediate code. /Jim -- Send compilers articles to compilers@esegue.segue.boston.ma.us {spdcc | ima | lotus}!esegue. Meta-mail to compilers-request@esegue. Please send responses to the author of the message, not the poster. Brought to you by Super Global Mega Corp .com