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Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!oakhill!dover!darla!waters
From: waters@darla.sps.mot.com (Strawberry Jammer)
Newsgroups: comp.lsi,comp.lsi.cad
Subject: Re: Circuit Simulator Benchmarks (also >= gate level)
Keywords: simulation benchmarks EDIF ELLA VHDL
Message-ID: <1958@dover.sps.mot.com>
Date: 28 Nov 89 16:00:57 GMT
References: <5780@alvin.mcnc.org> <61.256c4a76@manse.cad.cs.man.ac.uk>
Sender: news@dover.sps.mot.com
Reply-To: waters@darla.sps.mot.com (Strawberry Jammer)
Organization: Hacker's haven
Lines: 55

In article <61.256c4a76@manse.cad.cs.man.ac.uk> whitaker@cs.man.ac.uk writes:

}> 2.  In SPICE compatabile netlist form.  (For lack of a more universal
}> standard)
}> 
}> 3.  Use a standard device model:  SPICE Level I, II, III, IV or BJT.
}> Many industrial circuits use custom device  models, which again
}> confuses comparisons.
}
}There seems to be an overlap of standards at the gate
}level and above.  The `standards' in effect in this country
}include:
}
}    VHDL,
}    ELLA and 
}    EDIF (logicmodel and netlist are probably applicable here)
}    Any others?????
}
}I would like to conduct an informal email survey to determine
}which of these languages are in use, and which could provide the
}greatest number of benchmark circuits. This would
}help me, and hopefully others, when trying to find/use benchmarks.
}
}Do you use one, or more, of these languages?
}Do you intend to switch to using one of these?
}Do you have any opinions as to which language a set of simulation
}benchmarks should use?

At Motorola we use both VHDL and EDIF in various groups for various purposes.
Our intent is to track the ANSI/ISO standards scene as far as coordination
between the two is concerned.

We use EDIF netlists in our ASIC work as the only input for our HD CMOS gate
array line and as at least an acceptable input for every other ASIC product.

As for the VHDL/ELLA tradeoff we take no position, other than to observe that
VHDL is more available in the US. Again our intent is to track the formal
standards activities coordinating the "overlap" between these standards.

For the basic models either ELLA or VHDL would seem to be good candidates,
but as far as I know the models beingdone today are in actually C code or an
equivalent which is not the intent of either ELLA or VHDL as far as I am
aware.

For the connectivity between models the EDIF netlist view is clearly (IMHO)
the choice since it can handle the entire connectivity problem in a manner
consistent with normal circuit level design.

I would suggest making contact with the IEEE/EIA committees working on the
VHDL/EDIF interaction schemes as well as the ELLA equivalent before making a
selection.


           *Mike Waters    AA4MW/7  waters@dover.sps.mot.com *
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