Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!uunet!ncrlnk!ncrcae!hubcap!chi
From: chi@unc.cs.unc.edu (Vernon Chi)
Newsgroups: comp.parallel
Subject: Re: scalability of n-cubes, meshes (was: IPSC Communications)
Summary: physical constraints on scalability apply to any topology
Keywords: iPSC Parallel hypercubes meshes torus scalability
Message-ID: <7222@hubcap.clemson.edu>
Date: 28 Nov 89 19:08:59 GMT
Sender: fpst@hubcap.clemson.edu
Lines: 25
Approved: parallel@hubcap.clemson.edu

It's not clear why you couldn't have transparent wrap-around on 3-D
meshes analogous to torus connected 2-D meshes.  In principal, the
one dimensional wrap scheme which avoids long wires for any array
size, e.g.,

                     _______   _______   __
                    /       \ /       \ /  \
                   X    X    X    X    X    X
                    \__/ \_______/ \_______/


where "X" represents a node, should generalize to 2- and 3-D meshes.

Following your discussion of physically embedding in 3 dimensions, however,
it's worth noting that any realizable technology for packaging depends
on a layered hierarchy of successively larger functional entities, e.g.,
IC carriers, PC boards, card cages, racks, multiple rack equipment bays,
etc.  In harsh reality of actually constructing a system, it's hard to
see how to avoid the inherently longer wires required by successively
higher packaging levels regardless of the interconnection topology.

This suggests that data locality may play as prominent a role in
scalability as interconnect topology.  Which might make 2- and 3-D
meshes look even better in the limit as compared to higher dimensional
topologies.


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