Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!rice!uw-beaver!Teknowledge.COM!unix!hplabs!hp-sdd!ncr-sd!ncrcae!hubcap!Ran
From: ran@cs.utah.edu (Ran Ginosar)
Newsgroups: comp.parallel
Subject: Re: IPSC Communications
Message-ID: <7253@hubcap.clemson.edu>
Date: 30 Nov 89 13:38:00 GMT
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Approved: parallel@hubcap.clemson.edu


In article <7210@hubcap.clemson.edu> boulder!foobar!grunwald@ncar.UCAR.EDU (Dirk Grunwald) writes:

   In a single phrase, ``fat wires''.  The argument being that 8 wires
   transmit the info. of 1 at 8x the speed.  Thus, the latency of the
   *last byte* (not first) decreases because of increased bandwidth. ...

It turns out that, at least in edge-cutting technologies, this is not
exactly true. The limiting factor in driving N wires OFF CHIP is the
power-speed product. It takes N times more power to drive N wires off
the I/O pins of the node-chip than a single one, assuming you're
driving them as fast as the technology lets you. Given a constant
amount of power to disipate, it takes N times longer (more slowly!) to
drive N wires than one. While Dally's constancy factor, bisection
width, was key to the ongoing discussion, the constant power-speed
factor was overlooked.

Incidentally, the point was made (I believe) by Peter Denyer in his
1982 paper on bit-serial VLSI architectures, and by Richard Fujimoto
and Carlo Sequin (also 1982?) in their paper on X-trees and
Y-components. 
--
	Dr. Ran Ginosar			ran@cs.utah.edu
	Computer Science Department, University of Utah
	Salt Lake City, UT 84112.   Phone: 801-581-7705, fax 801-581-5843.


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