Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!usc!ucsd!ucsdhub!hp-sdd!ncr-sd!ncrcae!hubcap!wen-king From: wen-king@csvax.caltech.edu (Wen-King Su) Newsgroups: comp.parallel Subject: Re: IPSC Communications Message-ID: <7276@hubcap.clemson.edu> Date: 1 Dec 89 13:55:02 GMT Sender: fpst@hubcap.clemson.edu Lines: 35 Approved: parallel@hubcap.clemson.edu >From: ran@cs.utah.edu (Ran Ginosar) boulder!foobar!grunwald@ncar.UCAR.EDU (Dirk Grunwald) writes: > < In a single phrase, ``fat wires''. The argument being that 8 wires > transmit the info. of 1 at 8x the speed. Thus, the latency of the < *last byte* (not first) decreases because of increased bandwidth. ... > exactly true. The limiting factor in driving N wires OFF CHIP is the the I/O pins of the node-chip than a single one, assuming you're amount of power to disipate, it takes N times longer (more slowly!) to width, was key to the ongoing discussion, the constant power-speed a total of 4*sqrt(n) wires. The wire-count ratio of 2-D grid router to cube router is therefore 2*sqrt(n)/log2(n). The ratio becomes less than N (and keeps getting comparatively less) when n is greater than 16. We also have to take into account that many wires in a cube are long. We can overcome that difficulty by driving long wires as transmission lines (pump more than bits into a single wire before the first bit emerge from the other end of the wire, ie wave length of the data pulses is shorter than the wire length), but the cost and effort is probably more than the gain. /*------------------------------------------------------------------------*\ | Wen-King Su wen-king@vlsi.caltech.edu Caltech Corp of Cosmic Engineers | \*------------------------------------------------------------------------*/ Brought to you by Super Global Mega Corp .com