Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!uunet!ncrlnk!ncrcae!hubcap!stramm%beowulf From: stramm%beowulf@ucsd.edu (Bernd Stramm) Newsgroups: comp.parallel Subject: Re: IPSC Communications Summary: in the real world... Keywords: iPSC Parallel Message-ID: <7192@hubcap.clemson.edu> Date: 27 Nov 89 13:31:38 GMT Sender: fpst@hubcap.clemson.edu Lines: 34 Approved: parallel@hubcap.clemson.edu In article <7159@hubcap.clemson.edu> parker@vienna3.tmc.edu (Bruce Parker) writes: >In article <7142@hubcap.clemson.edu> pase@orville.nas.nasa.gov (Douglas M. Pase) writes: >> >>A lot of Intel's ideas are based (at least initially) on William Dally's PhD. >>thesis. >How is it possible for a sqrt(n) by sqrt(n) mesh with >O(sqrt(n)) diameter and bisection width to have lower >latency and contention than an n-node hypercube with O(lg n) >diameter and O(n) bisection? Is the analysis specialized >for certain problems as opposed to examining a worst- or >even average-case? It is possible if you consider wire length, communication word size, and bandwidth in the real world, i.e. in 2 or 3 dimensions. Since you have to map the hypercube to 3 dimensions, you get many long wires. Worse, you get many wires across a limited cross-section, so you have to make the communication word size smaller than if you use a 2 or 3 dimensional cube (or torus) with more elements in each dimension. He considers k-ary d-cubes (and tori), i.e. cubes of d dimensions with k elements along each dimension. For the number of PEs which are currently feasible, things work out best in 2 or 3 dimensions. For people seriously interested in parallel architecture, the thesis is well worth reading. It also investigates worm-hole routing, and presents the design and implementation of a self-timed routing chip (i.e. one that doesn't need a clock). >Bruce Parker Bernd Stramm UC San Diego stramm%cs@ucsd.edu or stramm@cs.ucsd.edu or bstramm@ucsd.bitnet Brought to you by Super Global Mega Corp .com