Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!usc!samsung!uakari.primate.wisc.edu!xanth!lll-winken!tekbspa!optilink!brad
From: brad@optilink.UUCP (Brad Yearwood)
Newsgroups: comp.sys.ibm.pc
Subject: Re: .84 usec Timer resolution on PC (actually jmp $+2)
Message-ID: <2685@optilink.UUCP>
Date: 30 Nov 89 08:04:32 GMT
References: <3056@cbnewsl.ATT.COM>
Distribution: usa
Organization: Optilink Corporation, Petaluma, CA
Lines: 36

From article <3056@cbnewsl.ATT.COM>, by saify@cbnewsl.ATT.COM (saify.lanewala):
> In article <1757@crdos1.crd.ge.COM>, davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr) writes:
>> In article <25235@sequent.UUCP> norsk@sequent.UUCP (Doug Thompson) writes:
>> 
>> | To program Timer 0 to Mode 2 do the following:
>> | 
>> | 	jmp 	$+2
>> 
>>   Could you explain the "jmp $+2" instructions? I mean, I know what they
> 
> That instruction is intended to flush the pre-fetch queue.  I read that
> somewhere, but cannot give more insight.  Perhaps some hardware guru .....

The immediate consequence of jmp $+2 is indeed to flush the prefetch queue.
The actual intent is to prevent I/O read or write cycles from proximate IN or
OUT instructions from being presented to a peripheral chip in too-rapid
succession.  Many of the PC peripheral chips (interrupt controllers etc.) date
back to the days of slow processors such as the 8085.  Frequently, they
require a command recovery time of a couple of microseconds or so after
accepting a command write or status read before they can handle another
operation.

The efficient instruction prefetch, decode, and execution queue of the '286
and '386 can result in multiple I/O read or write cycles occurring in immediate
succession.  The jmp $+2 flushes the pipeline, thereby forcing at least one
intervening memory cycle (an instruction fetch for the target instruction of
the jump) to some address other than the peripheral chip.  With the classic
6MHz AT, the resulting delay was sufficient to meet the peripheral chip's
command recovery time.  Of course, with a 25MHz 386 and perhaps a cache in
today's machines, one must take care that jmp $+2 is really sufficient for
the particular peripheral chip in the fastest possible case.  It might be
necessary to do several jmp $+2 (or some other delay maneuver).

Brad Yearwood
Optilink Corp.  {pyramid, tekbspa, pixar}!optilink!brad
Petaluma, CA