Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!tut.cis.ohio-state.edu!pt.cs.cmu.edu!andrew.cmu.edu!js7a+ From: js7a+@andrew.cmu.edu (James Price Salsman) Newsgroups: comp.sys.transputer Subject: Re: H1 transputer: Code compatible?!? Message-ID: Date: 29 Nov 89 12:59:28 GMT References: <8911282053.AA06866@tcgould.TN.CORNELL.EDU> Organization: Psychology, Carnegie Mellon, Pittsburgh, PA Lines: 25 In-Reply-To: <8911282053.AA06866@tcgould.TN.CORNELL.EDU> STORZ@EMBL.BITNET writes: > - virtual links (routing in hardware) Yes. Keeping this backward-compatible is going to require stressful contortions on the part of many designers... > - internal RAM (used like before or switched as fast CACHE) Only 2K instead of 4K. > - commands for fast 'standard' languages like C Dunno. I sure hope they come up with somthing faster than the "lend" instruction for tight inner toops, though. > - (perhaps MMU ???) Yes, designed to run Unix. Also static column mode DRAM addressing. > Somewhere else I heard about 6 links ? Nope, only TWO!!! Kinda defeats the purpose. The H-1 is definetly going to be a linear array. The funny thing is that it seems very much like the iWarp being developed here. I'm soooo confused. ----- :James Salsman (js7a+@andrew.cmu.edu) ::Carnegie Mellon