Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wuarchive!cs.utexas.edu!uunet!convex!hamrick@convex.COM
From: hamrick@convex.COM (Ed Hamrick)
Newsgroups: comp.arch
Subject: Intel 860 Architecture
Message-ID: <3818@convex.UUCP>
Date: 9 Dec 89 20:52:36 GMT
Sender: usenet@convex.UUCP
Reply-To: hamrick@convex.COM (Ed Hamrick)
Organization: Convex Computer Corporation, Seattle, WA
Lines: 34

A few questions about the Intel 860 architecture:

1) The 860 doesn't seem to have any divide instructions, either integer
   or floating point.  It seems to depend on a floating point reciprocal
   instruction followed by a floating point multiplication.

   - What other architectures use reciprocal -> multiply for divide?

   - What are the numerical accuracy tradeoffs?

   - How many cycles does the reciprocal instruction take? Can it be
     pipelined?

2) How deep is the pipeline for 64 bit adds / multiplies? 32 bit?

3) What happens to the pipeline if there are page faults / exceptions
   during dual operation mode?  Does the pipeline advance one step
   per clock cycle, or one step per floating instruction?

4) Is is possible to do pipelined FP loads with non-unit stride?

5) Is it possible to do pipelined scatter/gather operations?

6) The 860 doesn't seem to have integer multiplication instructions,
   and also doesn't seem to have any integer to floating conversion
   instructions.  What are the best ways to do efficient integer
   multiplication with the 860?  Does this have something to do with
   the fmlow instruction?

All in all, it looks like a well thought out chip, with a lot of clever
architectural trade-offs to get everything on one chip.

Regards,
Ed Hamrick