Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!mailrus!ames!ncar!tank!cps3xx!reid
From: reid@cpswh.cps.msu.edu (Dr Richard J. Reid)
Newsgroups: comp.arch
Subject: Amd/Xilinx LCA's
Message-ID: <5781@cps3xx.UUCP>
Date: 13 Dec 89 14:49:59 GMT
Sender: usenet@cps3xx.UUCP
Reply-To: reid@cpswh.cps.msu.edu (Dr Richard J. Reid)
Organization: Dept. of Computer Science, Michigan State University
Lines: 7


Does anyone have information about the correspondence
between the configuration-bit-stream bit positions
and the actual memory-cell-enabled switch positions in the
physical layout of the Amd or Xilinx logic cell arrays?

Thanks.