Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!cs.utexas.edu!uunet!portal!atari!imagen!qmsseq!pipkins
From: pipkins@qmsseq.imagen.com (Jeff Pipkins)
Newsgroups: comp.sys.ibm.pc
Subject: Re: .84 usec Timer resolution on PC (actually jmp $+2)
Message-ID: <57@qmsseq.imagen.com>
Date: 4 Dec 89 17:43:01 GMT
References: <3056@cbnewsl.ATT.COM> <2685@optilink.UUCP>
Reply-To: pipkins@qmsseq.UUCP (Jeff Pipkins)
Distribution: usa
Organization: QMS Inc., Mobile, Alabama
Lines: 16

The IBM AT Tech. Ref. manual says that successive IN and OUT
instructions, which "lock the bus" can starve out DMA transfers.
Do any of you hardware guys know more about this?

It seems to me that if I were making an AT compatible machine that
was faster, it would have to run AT software WITHOUT MODIFICATION
in order to be anything but worthless.  This means that the designers
should compensate for only getting one Jmp short +2 instruction
between INs and OUTs.  Someone please tell me this is true.  While
you're at it, maybe you can tell me that it was all a mistake and
that IBM never really screwed up this bad in the first place... @;-)

Jeff Pipkins
pipkins@imagen.COM
I am not authorized to speak for anyone but me.  (That includes
my wife).