Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!sunybcs!boulder!rieman From: rieman@boulder.Colorado.EDU (John Rieman) Newsgroups: comp.sys.mac.hardware Subject: Re: SIMM schematic Message-ID: <14814@boulder.Colorado.EDU> Date: 12 Dec 89 22:41:38 GMT References: <976@ux.acss.umn.edu> Sender: news@boulder.Colorado.EDU Reply-To: rieman@boulder.Colorado.EDU (John Rieman) Distribution: usa Organization: University of Colorado, Boulder Lines: 45 Here's a message that came through comp.sys.mac a few months ago. I assume it's accurate, but I'm no expert. -j -------- From sunybcs!rutgers!att!alberta!ubc-cs!van-bc!ve7apu!spraggs Fri Mar 31 09:19:48 MST 1989 Article 33061 of comp.sys.mac: Path: boulder!sunybcs!rutgers!att!alberta!ubc-cs!van-bc!ve7apu!spraggs >From: spraggs@ve7apu.UUCP ( VE7ADE) Newsgroups: comp.sys.mac Subject: Re: SIMM pinout Message-ID: <296@ve7apu.UUCP> Date: 30 Mar 89 07:29:16 GMT References: <25017@amdcad.AMD.COM> Reply-To: spraggs@ve7apu.UUCP (John Spraggs - VE7ADE) Organization: Doug Lockhart VE7APU Richmond, B.C. Lines: 26 This is the pinout for a 1 Meg SIMM. I have shown the assignments for a 9 bit part for completeness. The ninth chip is missing on a Mac SIMM so these (*) are NC as well. A 256k part is NC on A9. I expect a 4 Meg part puts A10 on pin 19 and a 16 Meg one has A11 on pin 24. X ___ X Vcc CAS DQ1 A0 A1 DQ2 A2 A3 Vss DQ3 A4 A5 DQ4 A6 A7 .. continued in line X 1 15 X X _ ___ ___ X .. DQ5 A8 A9 NC DQ6 W Vss DQ7 NC DQ8 Q9 RAS CAS9 D9 Vcc X 16 * * * 30 Vcc = +5V Vss = ground DQ = Data I/O A = Address ___ ___ CAS = Column Address Strobe RAS = Row Address Strobe Since the Mac + at least does not pull down D9 or CAS9, by 9 SIMMs should not be used since these inputs can float through the mid voltage region. When this happens excessive current flows, causing over heating and possibly enough noise to corrupt data. John Spraggs