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From: sms@WLV.IMSD.CONTEL.COM (Steven M. Schultz)
Newsgroups: comp.arch
Subject: Re: PUSH on i8088/i80x86
Message-ID: <44042@wlbr.IMSD.CONTEL.COM>
Date: 15 Jan 90 16:36:38 GMT
References: <1261570140@<182DAVISTD@MSU> > <208300005@prism> <1990Jan15.064658.1816@waikato.ac.nz>
Sender: news@wlbr.IMSD.CONTEL.COM
Reply-To: sms@WLV.IMSD.CONTEL.COM.UUCP (Steven M. Schultz)
Organization: Contel Federal Systems
Lines: 20

In article <1990Jan15.064658.1816@waikato.ac.nz> ldo@waikato.ac.nz (Lawrence D'Oliveiro) writes:
>This problem with pre/post-decrementing of SP in the Intel CPUs--
>there's another chip family with this quirk too. The analogous
>sequence
>
>	mov	sp, -(sp)
>
>is supposed to give different results on different members of
>the PDP-11 family...
>
>Anybody else remember this? Or am I just showing my age?

	I remember it well.  This is the (in)famous "Z" error which the
	assembler uses to flag such instructions.  The pdp-11/44, 45, 70 do
	not suffer from this peculiarity but the 11/40 and members of the
	micro-pdp11 family do.
	do.

	Steven M. Schultz
	sms@wlv.imsd.contel.com