Path: utzoo!utgpu!jarvis.csri.toronto.edu!clyde.concordia.ca!uunet!n3dmc!johnl
From: johnl@n3dmc.UU.NET (John Limpert)
Newsgroups: comp.arch
Subject: Re: PUSH on i8088/i80x86
Message-ID: <871@n3dmc.UU.NET>
Date: 15 Jan 90 19:41:38 GMT
References: <1261570140@<182DAVISTD@MSU> > <208300005@prism> <1990Jan15.064658.1816@waikato.ac.nz>
Reply-To: johnl@n3dmc.UUCP (John Limpert)
Organization: N3DMC, Silver Spring, Maryland
Lines: 48

In article <1990Jan15.064658.1816@waikato.ac.nz> ldo@waikato.ac.nz (Lawrence D'Oliveiro) writes:
>This problem with pre/post-decrementing of SP in the Intel CPUs--
>there's another chip family with this quirk too. The analogous
>sequence
>
>	mov	sp, -(sp)
>
>is supposed to give different results on different members of
>the PDP-11 family. I may be wrong (it's been a while since I've
>programmed a PDP-11) but the behaviour might occur if you replace
>SP with any of the other registers, as well.
>
>Anybody else remember this? Or am I just showing my age?

You are correct.  The LSI-11 processor handbook had a handy
list of the differences in CPU implementation for the PDP-11
family.

Here is the note from the MACRO-11 manual:

	Certain special instruction/address mode
	combinations, which are rarely or never
	used, do not operate the same on all
	PDP-11 processors, as described below.

	In the autoincrement mode, both the JMP
	and JSR instructions autoincrement the
	register before its use on the PDP-11/40
	but not on the PDP-11/45 or PDP-11/10.

	In double operand instructions having
	the addressing form Rn,(Rn)+ or
	Rn,-(Rn), where the source and
	destination registers are the same, the
	source operand is evaluated as the
	autoincremented or autodecremented
	value, but the destination register, at
	the time it is used, still contains the
	originally intended effective address.

	The use of these forms should be
	avoided, since they are not compatible
	with the entire family of PDP-11
	processors.

-- 
John A. Limpert			I'm the NRA!
Internet: johnl@n3dmc.UU.NET	UUCP: uunet!n3dmc!johnl