Path: utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!usc!apple!vsi1!wyse!mips!hal!mark
From: mark@mips.COM (Mark G. Johnson)
Newsgroups: comp.arch
Subject: Cool CMOS at ECL speeds (?)
Message-ID: <34525@mips.mips.COM>
Date: 16 Jan 90 15:39:55 GMT
References: <105@zds-ux.UUCP>
Sender: news@mips.COM
Reply-To: mark@mips.COM (Mark G. Johnson)
Organization: MIPS Computer Systems, Inc.
Lines: 55

In article <105@zds-ux.UUCP> gerry@zds-ux.UUCP (Gerry Gleason) writes:
  >
  >But doesn't CMOS get just as hot when you start clocking it at ECL speeds.
  >Or if not as hot, close enough to have serious power and cooling problems.
  >

According to Intel, No.  And this isn't just religious dogma, they have
something that comp.arch all too often does not: measured data.  At their
ISSCC presentation on the i860 (a CMOS microprocessor having onboard CPU,
floating point, and cache memory) they said that some parts would run at
50 MHz and, at that clock rate, dissipate only 2.5 Watts*.  This is
considerably less power than either the B5000 (ECL SPARC) or the R6000
(ECL MIPS) burn at 80 MHz.  For a fair comparison you'd have to further
cut the CMOS power by a factor of three, since the i860 includes F.P. and
cache whereas the B5000 and R6000 are CPUs only.

Other data to take notice of: CMOS uP's will soon operate from 3.3 volts **
which will reduce power dissipation by a factor of 2.3  [ = (5/3.3)^2 ].
It's doubtful that merchant ECL will reduce VEE as quickly, because that
would mean giving up 3-level series gated logic, which is an extremely
useful and often-exploited feature of present ECL.

The ECL camp isn't sitting still, of course.  IBM and Unisys have been
using a variant called CML for years, which operates off 3.0 volts and
works just fine without series gating.  However the _power_ benefits
for ECL/CML scale as a linear function of voltage whereas in CMOS it's
a squarelaw function.

Another development is pin-for-pin, drop-in replacements foc VLSI ECL
gate arrays made in Gallium Arsenide.  Convex is using these pretty
extensively.  Vendors claim GaAs will go the same speed as ECL but burn
1/4 the power.

Opinion, not data, follows; flame-broil me if you must...
   On each project, chip engineers design their parts to fit within the
   power budget allocated for that chip.  That's why you can't take the
   power per transistor per megahertz of the 386, multiply it by the
   number of transistors on the i860 times the clock rate of the i860,
   and get the power dissipation of the i860.  The 386 and the 860 were
   each _designed_ for a particular power dissipation.  Apparently the
   860's goal was moderately low power; hat's off to R. Albers &co for
   getting it so low.
--------------------------------------------------------------------------

*  Of course these are measured data on a few units and Intel has to write
   the datasheet spec more conservatively, with the Gaussian distribution
   in mind.

** Note that 3/4 of the requirements for 3.3 volt operation were available
   in 1989: 3.3 volt ASICs, 3.3 volt memories, and 3.3 volt glue logic.

-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
	(408) 991-0208    mark@mips.com  {or ...!decwrl!mips!mark}