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From: slackey@bbn.com (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: Cool CMOS at ECL speeds (?)
Message-ID: <50985@bbn.COM>
Date: 16 Jan 90 19:09:29 GMT
References: <105@zds-ux.UUCP> <34525@mips.mips.COM>
Sender: news@bbn.COM
Reply-To: slackey@BBN.COM (Stan Lackey)
Organization: Bolt Beranek and Newman Inc., Cambridge MA
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In article <34525@mips.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>In article <105@zds-ux.UUCP> gerry@zds-ux.UUCP (Gerry Gleason) writes:
>  >But doesn't CMOS get just as hot when you start clocking it at ECL speeds.
>  >Or if not as hot, close enough to have serious power and cooling problems.
>According to Intel, No.  And this isn't just religious dogma, they have
>something that comp.arch all too often does not: measured data.  At their
>ISSCC presentation on the i860 (a CMOS microprocessor having onboard CPU,
>floating point, and cache memory) they said that some parts would run at
>50 MHz and, at that clock rate, dissipate only 2.5 Watts*.  This is

I wonder if the conditions under which they quote power are the same
as those under which they quote performance: all pipes full, dual
instruction mode, mul-accum instructions, graphics operations running?
I mean, dissipation is proportional to load capacitance, which is
going to be proportional to the number of nodes switching (ref: "halt
and catch fire" instruction).  Also, can it be that the faster chips
in a lot are faster due to lower capacitance?

PS the story I heard was Convex is using TTL-compatible GaAs PALs, not ECL.

:-) Stan