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From: aglew@oberon.csg.uiuc.edu (Andy Glew)
Newsgroups: comp.arch
Subject: Error checking on ALU operations
Message-ID: <AGLEW.90Jan17112637@oberon.csg.uiuc.edu>
Date: 17 Jan 90 19:26:37 GMT
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In-Reply-To: lamaster@ames.arc.nasa.gov's message of 16 Jan 90 23:15:42 GMT

This comes up on a regular basis.  Proceedings of the Symposia on Computer
Arithmetic regularly contain papers on error checking of functional units
like ALUs.  Here are a few I encountered:

%A Lo
%A Thanwastien
%A Rao
%T Concurrent Error Detection in Arithmetic and Logical
Operations Using Berger Codes
%J ARITH9
%P 233-240
%X Berger codes = bit or zero counting.
Arithmetic checks involves counting bits in internal carries
of adders and multipliers.
Opens up the "black box" of ALU internals.
Handles logic.

%T Error Detection and Correction for Addition and Subtraction
Through Use of Higher Radix Extensions of Hamming Codes
%A Robertson
%J ARITH8
%P 226-229
%X SECDEC code for addition modulo 4.
Binary Hamming codes.

%T On-line Error-Detectable High-Speed Multiplier
Using Redundant Binary Representation and Three-Rail Logic
%A Takagi
%A Yajima
%J IEEE Transactions on Computers
%V C-36
%N 11
%D Nov 1987
%X Uses redundant binary signed digit notation.
Binary tree structure of carry free adders internal to array.
Three rail logic for error detection.
Most of the paper devoted to error checking features.
--
Andy Glew, aglew@uiuc.edu