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From: toms@omews44.intel.com (Tom Shott)
Newsgroups: comp.arch
Subject: Re: Cool CMOS at ECL speeds (?)
Message-ID: <TOMS.90Jan17133644@omews44.intel.com>
Date: 17 Jan 90 18:36:44 GMT
References: <105@zds-ux.UUCP> <34525@mips.mips.COM>
Sender: news@omepd.UUCP
Organization: OME, INTeL Corp., Hillsboro, Oregon
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In-reply-to: mark@mips.COM's message of 16 Jan 90 15:39:55 GMT


In article <34525@mips.mips.COM> mark@mips.COM (Mark G. Johnson) writes:

   Opinion, not data, follows; flame-broil me if you must...
      On each project, chip engineers design their parts to fit within the
      power budget allocated for that chip.  That's why you can't take the
      power per transistor per megahertz of the 386, multiply it by the
      number of transistors on the i860 times the clock rate of the i860,
      and get the power dissipation of the i860.  The 386 and the 860 were
      each _designed_ for a particular power dissipation.  Apparently the
      860's goal was moderately low power; hat's off to R. Albers &co for
      getting it so low.


Both higher performance and level power dissipation for new processors are a
result of improved fabrication processes. Improved processes have smaller
feature sizes which result in 1M + transistor chips. It also means more
devices for the same Cap value. Thus higher performance with a flat power
curve.

Opinion On:

I don't speak for Intel. (Well, hardly ever). Data sheets often have a
maximum power dissipation. This number is arrived at by finding a group of
chips at the edge of passing specs. Then all the available test sets are
run on the chips at the conditions stated in the specs for DC values and
loads. The highest power consumption noted is used. Thus your mileage may
very depending on output loading, software, etc. I don't know how we arrive
at "typical" power dissipation.

Opinion Off:


--
-----------------------------------------------------------------------------
Tom Shott    INTeL, 2111 NE 25th Ave., Hillsboro, OR 97123, (503) 696-4520
	     toms@omews44.intel.com OR toms%omews44.intel.com@csnet.relay.com
	INTeL.. Designers of the 960 Superscalar uP and other uP's