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From: ecsv12@castle.ed.ac.uk (T Stiemerling)
Newsgroups: comp.arch
Subject: Re: Cool CMOS at ECL speeds (?)
Message-ID: <1662@castle.ed.ac.uk>
Date: 17 Jan 90 12:11:50 GMT
References: <105@zds-ux.UUCP> <34525@mips.mips.COM> <50985@bbn.COM>
Reply-To: ecsv12@castle.ed.ac.uk (T Stiemerling)
Organization: Edinburgh University Computer Science Department
Lines: 13

CMOS gates (inverters etc.) when constructed in regular `complementary'
fashion do not dissipate much heat since current only flows when there
is a change in the input, ie dynamic power dissipation only, whereas
NMOS for example dissipates power statically (one of the advantages of
CMOS).  CMOS is constructed using FET's while ECL is constructed from
bipolar transistors, which probably also dissipate heat statically
(although I'm not sure), leading to the greater heat dissipation and
power consumption of ECL devices over CMOS devices being clocked at the
same speed. 

-- 
Tom Stiemerling, Computer Science Department, Edinburgh University,
Edinburgh, UK. : 031-667 1081 : T.R.Stiemerling@uk.ac.edinburgh