Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!uakari.primate.wisc.edu!ames!ames.arc.nasa.gov!lamaster
From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.sys.m88k
Subject: Re: Information wanted on m88000 Risc workstations
Message-ID: <40837@ames.arc.nasa.gov>
Date: 18 Jan 90 17:26:05 GMT
References: <641@s5.Morgan.COM> <25A64468.11498@paris.ics.uci.edu> <648@s5.Morgan.COM> <1879@xyzzy.UUCP> <TOM.90Jan9101628@hcx2.ssd.csd.harris.com> <2811@yogi.oakhill.UUCP> <34446@mips.mips.COM> <2831@yogi.oakhill.UUCP> <34780@mips.mips.COM>
Sender: usenet@ames.arc.nasa.gov
Organization: NASA - Ames Research Center
Lines: 43

In article <34780@mips.mips.COM> earl@wright.mips.com (Earl Killian) writes:
>In article <2831@yogi.oakhill.UUCP>, marvin@oakhill (Marvin Denman) writes:
:
>What about double? ;-)
Good question.  I would like to see both single and double numbers, when
these comparisons come up.
>Anyway, the point of my response to the original
>	It will be interesting to see if MIPS goes to pipelining
>	floating point instructions in future parts.
>is that we're not going to add pipelining at the expense of latency,

I wonder what f.p. op counts are common these days.  For example, has anyone
done an analysis of the SPEC benchmarks to see what the (dynamic) instruction 
counts on various RISC machines are 
(like the ones we used to see for the IBM 360 :-)
and, also, what the sequences look like for things like the matrix-vector
version of Linpack (i.e. the most floating point intensive vectoriazable codes).

Conjecture:

I would guess that you will see some potential benefit to pipelining add, but
not multiply or divide (as long as you don't have vector instructions). 

Suggestion:

Consider pipelining add by duplication of the add unit.  I think this approach
has benefits:  

You can use the same already optimized adder design, and, 
most real-estate-saving pipelining methods add latency.  

I think MIPSCo is correct to reduce latency first, but
I think there will be usable speedup if add is pipelined, according to
instruction analyses that I have seen previously for other architectures. 

The Motorola and MIPSCo products each represent reasonable design choices.
It is interesting to have real competition in a product area which was
lunatic fringe three or four years ago.

  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117