Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!cornell!uw-beaver!rice!sun-spots-request
From: hplabs!sritacco@hpdml93.hp.com (Steve Ritacco)
Newsgroups: comp.sys.sun
Subject: Re: SPARC divide - really really slow!
Message-ID: <4323@brazos.Rice.edu>
Date: 10 Jan 90 21:58:27 GMT
Sender: root@rice.edu
Organization: Sun-Spots
Lines: 6
Keywords: Miscellaneous
Approved: Sun-Spots@rice.edu
X-Refs:  Original: v9n1
X-Sun-Spots-Digest: Volume 9, Issue 10, message 5 of 22

Well,  This really isn't the RISC strategy.  Check into some other RISC
chips and you will see better multiply and divide performance.  I think
the R2000/R2000 takes 12 cycles for multiply and 30 cycles for divide.
The multiply divide unit is seperate from the rest of the ALU so you are
also allowed to perform other operations while the multiply or divide are
going on.