Xref: utzoo sci.electronics:9407 comp.misc:7907 Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!tut.cis.ohio-state.edu!zaphod.mps.ohio-state.edu!sunybcs!boulder!ccncsu!ncr-fc!mikemc From: mikemc@mustang.ncr-fc.FtCollins.NCR.com (Mike McManus) Newsgroups: sci.electronics,comp.misc Subject: Re: Memory access time Message-ID: Date: 11 Jan 90 15:07:37 GMT References: <929@fs1.ee.ubc.ca> Sender: news@ncr-fc.FtCollins.NCR.COM Organization: NCR Microelectronic Products, Ft. Collins, CO Lines: 48 In-reply-to: vincel@fs0.ee.ubc.ca's message of 10 Jan 90 19:36:36 GMT In article <929@fs1.ee.ubc.ca> vincel@fs0.ee.ubc.ca (vincent li) writes: > The conclusion I've made is that the chip select usually controls the address > decoding units within the RAM and address decoding cannot begin until the > CS is asserted. Not necessarily so. It may happen that in some designs, the CS does not gate the address input (altho, *USUALLY* this is so), but instead may simply gate (or tristate) the outputs of the RAM/ROM. > The access time is the time when the address into the RAM > start getting decoded to when the valid data from the memory matrix appears > or can appear on the data bus. Thus, I believe you should use the tAA if > CS is asserted BEFORE the address is valid, and use tACS otherwise, but am > not sure. What you really need to do is to use the parameter that gives the worst-case read time. For example, if tAA is spec'ed at 20nS and tCS is 25nS, then even if CS is asserted 3nS before the address is valid, the read time is still defined by tCS = 25nS. One thing to keep in mind is that in most memory systems, the CS are made from high-order address bits. In other words, in a system which has 64K of memory (but who would want to work on such a system? :-), there would be 16 address lines to decode. Assume that the system uses 16K RAM chips. This would require 14 address lines to go to each chip, with 4 address lines left over to be decoded and used as chip selects. The time that it takes to decode the address lines to get the CS signals would obviously be critical. But, to simplify, assume that this decode could happen instantaneously (in fact, using some ROM/RAM chips that provide multiple CS's, a small system like this could be build without the extra CS decode circuitry). Then the *REAL* read access time is simply MAX( tAA, tCS). In the non-simplified case, it is MAX( tAA, tCS + CS decode overhead). Of course, not all architectures use this scheme, but it is common in simpler systems. Hope this helps! -- Disclaimer: All spelling and/or grammer in this document are guaranteed to be correct; any exseptions is the is wurk uv intter-net deemuns. Mike McManus (mikemc@ncr-fc.FtCollins.ncr.com) NCR Microelectronics 2001 Danfield Ct. mikemc@ncr-fc@ncr-sd.sandiego.ncr.com, or Ft. Collins, Colorado mikemc@ncr-fc@ccncsu.colostate.edu (303) 223-5100 Ext. 360 (they're ugly, but they work!)