Xref: utzoo sci.electronics:9437 comp.misc:7915
Path: utzoo!attcan!uunet!samsung!think!mintaka!oliveb!pyramid!ctnews!netcom!hue
From: hue@netcom.UUCP (Jonathan Hue)
Newsgroups: sci.electronics,comp.misc
Subject: Re: Memory access time
Message-ID: <5597@netcom.UUCP>
Date: 12 Jan 90 08:28:11 GMT
References: <929@fs1.ee.ubc.ca>
Organization: NetCom- The Bay Area's Public Access Unix System {408 249-0290 guest}
Lines: 21

In article <929@fs1.ee.ubc.ca> vincel@fs0.ee.ubc.ca (vincent li) writes:
>These are for the read cycle. So, in calculations, do I use tACS or tAA?
>The conclusion I've made is that the chip select usually controls the address
>decoding units within the RAM and address decoding cannot begin until the
>CS is asserted.

You should be able to tell from the block diagram on the data sheet if this
is the case (it usually is).  Most parts I've used use /CS for gating row and
column address, and the input for writes.

	 The access time is the time when the address into the RAM
>start getting decoded to when the valid data from the memory matrix appears
>or can appear on the data bus. Thus, I believe you should use the tAA if
>CS is asserted BEFORE the address is valid, and use tACS otherwise, but am
>not sure.

For most parts I've used the two are spec'd at the same value.  tAA
(or tACC, as I've seen it, your tACS I've seen called tCO) is for when
you're continuously holding /CS low.

-Jonathan