Xref: utzoo sci.electronics:9470 comp.misc:7927
Path: utzoo!attcan!uunet!cs.utexas.edu!usc!apple!oliveb!pyramid!leadsv!practic!vlsisj!davidc
From: davidc@vlsisj.VLSI.COM (David Chapman)
Newsgroups: sci.electronics,comp.misc
Subject: Re: Memory access time
Message-ID: <15436@vlsisj.VLSI.COM>
Date: 12 Jan 90 05:49:31 GMT
References: <929@fs1.ee.ubc.ca>
Reply-To: davidc@vlsisj.UUCP (David Chapman)
Organization: VLSI Technology Inc., San Jose, CA
Lines: 28

In article <929@fs1.ee.ubc.ca> vincel@fs0.ee.ubc.ca (vincent li) writes:
>Hello folks. I am developing an expert advisor for my thesis and is confused on
>the following piece of knowledge on (static) memory. On most memory data sheets
>the *access time* of the data is usually given by two parameters:
>tAA - address access time, time when address is valid to data is valid
>tACS - chip select access time, time when chip select is asserted to when
>data is valid.

Static RAM chips are supposed to be asynchronous devices.  If CS is active,
the outputs are supposed to be the data for whatever address is on the inputs.
tACS is probably the time required to turn on the bus drivers and tAA is the
time it takes to read data after an address changes.  For fast SRAMs (i.e.
all recent chips) these are often the same order of magnitude.  For 250 ns
SRAMs, for example, tCS should be much less than tAA.

Note that this means that if the address lines change while CS is active,
the data outputs will change a maximum of tAA later.  Output data is NOT
latched by CS going active!

With respect to your modelling:  data will be valid at the *later* of: 
(address lines stable + tAA) or (CS active + tACS).  There is probably
yet another time associated with the read signal going active.  The same
principle applies.
-- 
		David Chapman

{known world}!decwrl!vlsisj!fndry!davidc
vlsisj!fndry!davidc@decwrl.dec.com