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From: tim@nucleus.amd.com (Tim Olson)
Newsgroups: comp.arch
Subject: Re: Floating point register renaming (really: scoreboards & Alice .. (long))
Message-ID: <29515@amdcad.AMD.COM>
Date: 15 Mar 90 23:32:09 GMT
References: <3090@elmer.oakhill.UUCP> <37065@mips.mips.COM>
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Reply-To: tim@amd.com (Tim Olson)
Organization: Advanced Micro Devices, Inc., Austin, Texas
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In article <37065@mips.mips.COM> keith@mips.COM (Keith Garrett) writes:
| In article <3090@elmer.oakhill.UUCP> michaelb@oakhill.UUCP (Mike Becker) writes:
| >Calling the R3000 load a 1-cycle load is "just marketing silliness, confusing,
| >and contradictory to terminology long-used in computer architecture."  This
| >usage suggests that the load has the same execution time as an integer add.
| 
| load and store instructions spend the same amount of time in each of the same
| pipeline stages as any of the other 1-cycle instructions. The only difference
| is that the result of load instructions is available one cycle later than
| the result of alu ops would be (ie. a one cycle load delay). loads to not
| stall the pipe except for cache misses. perhaps you are thinking of some other
| architecture :?>

Yes, loads and stores have single-cycle issue rate in the MIPS
pipeline, but they have a 2-cycle latency.  This is what most people
refer to when talking about the cycle time of operations without
further specifying them.

	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)