Path: utzoo!attcan!uunet!snorkelwacker!apple!baum
From: baum@Apple.COM (Allen J. Baum)
Newsgroups: comp.arch
Subject: Re: Dynamic internal state (was Re: Scoreboards / Load-interlocks)
Message-ID: <39538@apple.Apple.COM>
Date: 16 Mar 90 19:17:46 GMT
References: <11337@encore.Encore.COM> <3300106@m.cs.uiuc.edu> <32937@shemp.CS.UCLA.EDU> <132903@sun.Eng.Sun.COM>
Reply-To: baum@apple.UUCP (Allen Baum)
Organization: Apple Computer, Inc.
Lines: 17

[]
>In article <132903@sun.Eng.Sun.COM> petolino@sun.UUCP (Joe Petolino) writes:
 I saw an interesting idea
>in a paper about the SPUR cache - it proposed using dynamic RAM cells for an
>on-chip I-Cache (to save area),

If it's what I'm thinking of, its a cute idea. Guarantee that the 'valid' bit
decays before any of the others, and its easy.

>Latches *are* static, at least the ECL ones that you'd find in a Cray.

Many of the latches found in CMOS are not. Its quite common to make a master-
slave flip-flop out of a dynamic stage, and a static stage. Then, the clock can
be stopped (but only during one of the phases).
--
		  baum@apple.com		(408)974-3385
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