Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!samsung!uunet!zds-ux!gerry
From: gerry@zds-ux.UUCP (Gerry Gleason)
Newsgroups: comp.arch
Subject: Re: Indirect addressing on SIMD architectures
Message-ID: <222@zds-ux.UUCP>
Date: 16 Mar 90 20:39:15 GMT
References: <8332@hubcap.clemson.edu> <1080@m1.cs.man.ac.uk>
Reply-To: gerry@zds-ux.UUCP (Gerry Gleason)
Organization: Zenith Data Systems
Lines: 22

In article <1080@m1.cs.man.ac.uk> mshute@r4.UUCP (Malcolm Shute) writes:
|What you have described seems to me to be a description of any SISD
|machine which can be implemented using bitslicing.  There's nothing
|wrong in that, of course.  My question to the net is, however, what is
|the value of the classification scheme if we can lump all bitwise-parallel
|von Neumann computers into the SIMD slot.

|Viewed the other way, if all of the processors access memory addresses
|in strict harmony like this, then they are only biting off parts of
|the *same* data stream.  (And hence all qualify as being SISD).
|Surely, it is only the MAMD machines which you mentioned later
|which can claim to qualify as true SIMD.

If I understand you correctly, you are missing an important part of
(at least some) SIMD architectures.  Take TMI's connection machine;
it has and interconnection network that can permute a word from each
processor to any other processor in a constant amount of time (well,
not quite, there is a factor of log2(number of PE's) in the equation,
but constant for a given machine size).  This network is a very important
part of the computational capacity of the machine.

Gerry Gleason