Path: utzoo!attcan!uunet!snorkelwacker!mit-eddie!bbn!bbn.com!slackey
From: slackey@bbn.com (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: Killer Micros and the TC2000
Message-ID: <53795@bbn.COM>
Date: 20 Mar 90 15:04:40 GMT
References: <51771@lll-winken.LLNL.GOV> <100598@convex.convex.com> <52661@lll-winken.LLNL.GOV> <798@dgis.dtic.dla.mil> <45408@ames.arc.nasa.gov>
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Reply-To: slackey@BBN.COM (Stan Lackey)
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In article <45408@ames.arc.nasa.gov> lamaster@ames.arc.nasa.gov (Hugh LaMaster) writes:
>Speaking of architectural issues, how is the BBN TC 2000 working out?
>It should be a perfect example of Killer Micros in action.  But,
>I was rather surprised that the TC 2000 Butterfly switch is only 8 bits (!)
>wide and only supports a maximum memory bandwidth of 2.4 GBytes/sec
>for a 63 processor system.  A Cray Y-MP has about 40 GBytes/sec of total
>memory bandwidth, for reference.

The peak bandwidth of the 63-node TC2000 depends upon where you
measure it.  The memory has a 3-level hierarchy: 1) cache, 2)local
memory, and 3)global memory.  The Cray has no cache, but the 88000
chip set does; the appropriate place to measure would probably be at
the busses between the CPU chip and the cache chips.  Combined
instruction cache and data cache bussus are a peak of 160 MB/s, times
63 processors is 10 GB/s.  Local memory speed is in the neighborhood
of 25 MB/s, times 63 or 1.5 GB/s.  Global memory is 8 MB/s for an
aggregate of 500 MB/s.  Your mileage will be somewhere between 10 GB/s
and 500 MB/s, depending upon cache hit rate and the mixture of
accesses between local and global memory.

The 8-bit switch path clocks at 38 MHz, so the raw bandwidth of the
media is 38 MB/s.  Times 63 paths is peak media speed of 2.4 GB/s.

Not to mislead, the above describes more the performance model, with
the speed differential between local and global memory.  The
programming model is a single globally addressed memory space.
-Stan