Path: utzoo!attcan!uunet!mailrus!bbn!bbn.com!slackey
From: slackey@bbn.com (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: Killer Micros and the TC2000
Message-ID: <53818@bbn.COM>
Date: 20 Mar 90 19:36:17 GMT
References: <51771@lll-winken.LLNL.GOV> <100598@convex.convex.com> <52661@lll-winken.LLNL.GOV> <798@dgis.dtic.dla.mil> <45408@ames.arc.nasa.gov> <53795@bbn.COM>
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Reply-To: slackey@BBN.COM (Stan Lackey)
Organization: Bolt Beranek and Newman Inc., Cambridge MA
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In article <53795@bbn.COM> slackey@BBN.COM I responded to a posting
comparing TC2000 and Cray memory bandwidths:
>The peak bandwidth of the 63-node TC2000 depends upon where you
>measure it.  The memory has a 3-level hierarchy: 1) cache, 2)local
>memory, and 3)global memory.
I included a set of approximate peak bandwidths at the various levels,
commenting on what I felt was an apples-to-oranges comparison with the
Cray.  I erroneously left out the disclaimer: These are approximate
peak values given for comparison with other architectures only.
Although these values can be achieved under certain circumstances,
delivered averages will vary depending upon the application.
-Stan