Path: utzoo!attcan!uunet!sco!seanf
From: seanf@sco.COM (Sean Fagan)
Newsgroups: comp.arch
Subject: Re: Why The Move To RISC Architectures?  ('386 vs. RISC)
Message-ID: <5303@scolex.sco.COM>
Date: 21 Mar 90 13:21:00 GMT
References: <28012@cup.portal.com> <1990Mar20.175843.2612@utzoo.uucp>
Sender: news@sco.COM
Reply-To: seanf@sco.COM (Sean Fagan)
Organization: The Santa Cruz Operation, Inc.
Lines: 46


In article <1990Mar20.175843.2612@utzoo.uucp> henry@utzoo.uucp (Henry Spencer) writes:
>The fact is, trying to bundle
>zillions of instructions onto the chip usually makes them slower, and
>compilers find it very difficult to effectively exploit all the bizarre
>silliness that CISC designers throw in.  

Time to throw myself into the fray (and mention Seymour and CDC later, too
8-)).  Simple, non-hardware engineer reason why what Henry says is true
(and, for the most part, it *is* true):  you have only a finite amount of
silicon space on a chip.  Given that, you have a couple of options:  you can
make a small amount of instructions *really* fast (through the brute force
method of just throwing silicon at it), or you can make a large amount of
instructions (which might be fast, or might not; since you now have less
silicon, they will probably be slower).  You can, within limits, make any
instruction faster by throwing more silicon at it.  For example, you can do
a 32x32->64 (bit) multiply in 2 cycles if you use enough silicon, maybe even
one cycle.  This will, however, take up *lots* of chip space, so you might
just keep it down to somewhere between 2 and 5 cycles, or get rid of it
entirely (since you can do any multiply with shifts and adds, and a large
amount of multiplies in certain test sets use mostly constants).  If you've
made all of your instructions execute as fast as possible, and have more
space available, you can have, oh, an on-board MMU, on-board FPU, on-board
cache, second processor, etc.  With larger instruction sets, you don't have
that option as much.

After you've done all that, btw, you can throw in pipelining if you don't
already have it, multiple functional units, scoreboarding (either full or
the simpler one most people use), etc.  Meanwhile, the CISC chip is still
trying to make the POLY instruction execute in something less than 100
cycles...

>About a decade ago, it started
>to become clear that executing simple instructions very quickly works
>much better.

Well, I'd say more than that, about 25 years.  Seymour Cray and the CDC
Cyber 6600, a truly wonderful machine with less than 74 instructions, a
load-store architecture, and three-operand instructions.  Just beautiful.

-- 

-----------------+
Sean Eric Fagan  | "Time has little to do with infinity and jelly donuts."
seanf@sco.COM    |    -- Thomas Magnum (Tom Selleck), _Magnum, P.I._
(408) 458-1422   | Any opinions expressed are my own, not my employers'.