Path: utzoo!attcan!uunet!crdgw1!CRD.GE.COM
From: oconnordm@CRD.GE.COM (Dennis M. O'Connor)
Newsgroups: comp.sys.amiga
Subject: Re: 68040 (Was Re: Amiga 3000)
Message-ID: <6127@crdgw1.crd.ge.com>
Date: 16 Mar 90 19:12:35 GMT
References: <13479@baldrick.udel.EDU> <9884@batcomputer.tn.cornell.edu> <100578@convex.convex.com> <5812@tekig5.PEN.TEK.COM> <10216@cbmvax.commodore.com>
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Reply-To: oconnordm@CRD.GE.COM (Dennis M. O'Connor)
Followup-To: comp.arch
Organization: GE Corporate R&D Center
Lines: 23
In-reply-to: daveh@cbmvax.commodore.com (Dave Haynie)

daveh@cbmvax (Dave Haynie) writes:
] [...]  But with cache access time the same as register access time,
] the need for more registers is greatly reduced, while at the same time
] maintaining compatibility.

This is all true of course. Comment : given a cache is as fast as
the registers, the registers still have a few advantage left over
memory locations : they are usually addressable in fewer bits, and
new results in them aren't written externally unless neccesary. (The
latter is sometimes an advantage :) And they don't need tag storage.

So, don't look for fast cache to make registers obsolete !
Memory-to-memory architecture ? Well, good effort, guys, good effort !

('round these parts, we use "good effort" to encourage people
 on the other team when they make mistakes, hoping to train them
 into making more :-)`

Follow-ups to comp.arch.
--
  Dennis O'Connor      OCONNORDM@CRD.GE.COM      UUNET!CRD.GE.COM!OCONNOR
  "Let's take a little off the top ... a bit off the sides ...
    trim the back a bit ... Surprise ! You've been bald-ed !"